Field programmable gate arrays (FPGAs) are user programmable logic devices formed in integrated circuit chips, which include within them configurable logic blocks and a configurable interconnect structure. By configuring the chip, the logic blocks can each be made to perform a selected one of many functions, and the interconnect can be connected to route signals from one logic block and to points exterior to the chip. Thus the FPGA can be programmed or configured to perform a desired complex function and provide output signals at selected exterior pins as specified by the user. Some FPGAs are non-volatile and one-time programmable. Others are reprogrammable. Some have logic blocks configured by applying particular signals to logic gate inputs or multiplexer control inputs. Others are configured by applying a combination of signals to logic gate inputs or multiplexer controls and loading a sequence of bits into a memory. The memory provides a logic function of signals on memory address lines, the function being determined by the set of values loaded into the bits of the memory. Such devices are manufactured by Xilinx, Inc., assignee of the present invention, and are described more thoroughly in the 1992 "The Programmable Gate Array Data Book" available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Such devices are also described in U.S. Pat. Nos. 4,870,302, and 4,706,216 incorporated herein by reference. FIG. 8 of the '216 patent in particular, describes a logic block which is configured by loading bits in a memory and configuring certain multiplexers, exclusive-or gates and AND gates to respond in particular ways to other input signals.
FIG. 1 shows a logic block of the type discussed in U.S. Pat. No. 4,706,216. 8-bit RAM 108 provides a configurable function of the address bits A, B, and C on lines 110-1, 110-2, and 110-3 respectively. Multiplexers 112, 113, 114, 123,126, 127, and 128 determine whether one of the 8 bits in RAM 108 will be forwarded. XOR gates 124, 129, and 130 determine whether the outputs of multiplexers 123, 127, and 128 respectively will be inverted, and AND gates 125, 131, and 132 determine whether the respective outputs of the XOR gates will be passed to a terminal of storage device 121. In order to select the desired option, a control signal must be provided to each of these multiplexers, XOR gates and AND gates. Thus, a means of storing the signal must be provided, such as a memory cell.
In FIG. 1, a second 8-bit RAM 109 can also be configured to provide another function of the inputs A, B and C. Input signal D causes multiplexer 112 to select between the two functions. Thus the logic block of FIG. 1 can provide a selectable function of the inputs A, B, C, and D. It frequently occurs that a user may partition logic into the chip so that only three inputs, for example A, B, and C are used in a particular logic block, and that the D input is not used (tied to a constant value rather than connected to receive a logic signal). In this case it is not necessary to use both 8-bit RAMs 108 and 109 since either RAM could provide all functions of three inputs. Thus some silicon area which has been dedicated to the second 8-bit RAM is not used.